Cerebras announced the CS-4 on Tuesday, August eighteenth, 2026, and the number it leads with is 750 petaflops of AI compute in a single rack, roughly six times what one CS-3 lists. The interesting part is where that gain comes from, because it is not a new chip. The wafer inside is the same WSE-3 design with the same four trillion transistors, run faster and packaged three to a rack. This is a systems release dressed as a silicon release, and for anyone who plans inference capacity the packaging details matter more than the headline figure. Here is what changed, and what it means for your network fabric.
The short answer
Cerebras announced the CS-4 on Tuesday, August eighteenth, 2026. Three WSE-3 Turbo wafers sit in one rack for 750 petaflops of AI compute, 129.6 petabytes per second of aggregate memory bandwidth and 7.2 terabits per second of system I/O. The wafer itself is not new. It is the existing WSE-3 run faster, with the rest of the gain coming from packaging three of them together. First shipments are expected during the third quarter of 2026, and pricing has not been published.
Most accelerator launches ask you to wait for a new process node. This one did not, and that is the part worth reading twice.
What was announced
Cerebras unveiled the CS-4 on Tuesday, August eighteenth, 2026. It is the company's first multi wafer system, and the specifications it published are rack level rather than per chip.
The rack lists 750 petaflops of AI compute, 129.6 petabytes per second of aggregate memory bandwidth, and 7.2 terabits per second of system I/O. Three WSE-3 Turbo wafer scale engines sit inside. Wafer to wafer latency is quoted as low as 2 microseconds, against roughly 5 microseconds on the previous CS-3. The company says the design addresses models beyond 50 trillion parameters, and that first shipments arrive during the third quarter of 2026. No price was given.
The performance claims are all comparative. Up to twice the speed of a CS-3 per wafer. Up to six times the compute of one CS-3 at rack level. Up to ten times higher throughput per watt than a CS-3. And up to thirty times more tokens per second per user than what the company calls leading GPU solutions, with a stated figure of more than 4,400 tokens per second per user on GPT-OSS-120B.
Chief executive and co founder Andrew Feldman framed it around a tradeoff, saying that historically fast inference meant using smaller models, and that CS-4 delivers those speeds on the largest frontier models instead. Chief technology officer Sean Lie was more specific about who benefits, noting that being thirty times faster gives agentic systems room for substantially more reasoning, verification or tool use in the same wall clock time.
The chip did not change
Here is the detail that most coverage buried. WSE-3 Turbo is the WSE-3.
Same four trillion transistors. Same 900,000 AI cores. Same 44 GB of SRAM sitting on the wafer itself. Same 5 nm TSMC process. Cerebras is not claiming a new die, and it says plainly where the extra speed comes from, which is closer power delivery and a redesigned cooling, I/O and control assembly.
That is a meaningful engineering result rather than a marketing dodge. A wafer scale part is limited by how much current you can get into it and how much heat you can pull out of it, long before it is limited by the transistors. Improving both lets you run the same silicon harder. It is the same reason a well cooled server CPU holds its turbo clocks while a badly cooled one drops them within seconds, scaled up to a piece of silicon the size of a dinner plate.
Doing the arithmetic on the headline is worthwhile. Six times per rack breaks down as roughly two times from running each wafer faster and three times from putting three wafers where there used to be one. Only the first half is a silicon story. The second half is a rack story, and rack stories come with power and cooling consequences that show up in your facility rather than on a spec sheet.
Nexus, and the part that touches your network
The CS-4 introduces what Cerebras calls the Nexus Platform Architecture. Three pieces are worth knowing about.
The first is a pluggable Wafer-Scale Backpack, the modular assembly carrying power, cooling and control for each wafer. Making that a serviceable module rather than a welded in subsystem is what allows three wafers to share one rack without the whole thing becoming a single unrepairable object.
The second is Direct Wafer Links, the interconnect between the three wafers. This is where the 2 microsecond figure lives. It is a private link, it is Cerebras business, and you will never configure it.
The third is the one to pay attention to, a programmable I/O subsystem speaking RoCE v2. RDMA over Converged Ethernet version two is routable RDMA on ordinary Ethernet, which means the system attaches to a fabric your team already knows how to build, rather than to InfiniBand or something proprietary.
That has practical consequences. RoCE v2 works properly on a lossless fabric, which in most designs means priority flow control on the RDMA class of service and explicit congestion notification configured end to end, with matching settings on every switch in the path. Get it wrong and you do not get an error, you get pause storms and collapsed throughput that look like an application problem for a week. Anyone who has stood up NVMe over Fabrics or a GPUDirect cluster has done this work before, and the same runbook applies here. Being able to reuse it is a genuine operational saving, and it is the reason the RoCE v2 line matters more to a network team than the petaflops figure does.
What to hold at arm's length
Thirty times faster than a GPU is a vendor comparison against an unnamed configuration, and the honest reading is that it applies to tokens per second per user on a specific model rather than to anything you could put on a purchase order.
That distinction is the whole argument. Tokens per second per user is a single stream decode measurement, and it is exactly what an agent loop is bound by, since planning, calling a tool and rechecking output all happen in sequence. Aggregate throughput across many concurrent requests is a different number, and it is the one that sets your cost per million tokens. A system can win decisively on the first while being unremarkable on the second. Cerebras is choosing to compete on the metric that suits agentic workloads, which is a defensible strategy and also a selective one.
The other caution is timing. First shipments are expected this quarter, which means no independent benchmark exists yet from anyone who is not selling the machine. The same reservation applied when OpenAI previewed a fast serving tier built on this class of hardware, and it applies again here. The broader trend the CS-4 sits inside, of specialising hardware around the distinct phases of inference rather than running everything on identical parts, is visible across the industry and turned up again when AMD and Cerebras split inference across two chip types. That direction looks solid. The individual multipliers deserve your own measurements.
Sources and further reading
- Cerebras Unveils CS-4: Up to 30 Times Faster than GPU-based Solutions, GlobeNewswire via The Manila Times, August 19, 2026
- Cerebras launches CS-4 for faster AI inference, Techzine, August 19, 2026
- Cerebras launches the CS-4, its first multi-wafer system, though the chip inside is not new, TNW, August 2026
- Cerebras debuts CS-4 AI accelerator with new wafer-scale architecture, Verdict, August 2026
Frequently asked questions
What are the CS-4 headline specifications?
Cerebras lists 750 petaflops of AI compute at rack level, 129.6 petabytes per second of aggregate memory bandwidth, and 7.2 terabits per second of system I/O. The rack holds three WSE-3 Turbo wafer scale engines. Each wafer keeps the four trillion transistors, 900,000 AI cores and 44 GB of on wafer SRAM of the existing WSE-3, built on a 5 nm TSMC process. Wafer to wafer latency drops to as low as 2 microseconds, against roughly 5 microseconds on the CS-3. The company says the system addresses models of more than 50 trillion parameters. First shipments are expected during the third quarter of 2026. Pricing has not been published.
Is the CS-4 a new generation of silicon?
No, and Cerebras does not claim otherwise. The wafer is called WSE-3 Turbo, which is the existing WSE-3 die running at a higher operating speed. The company attributes the extra speed to closer power delivery and a redesigned cooling, I/O and control assembly rather than to a new process node or a new core design. Per wafer, the claim is about twice the speed of a CS-3 wafer. The other three times comes from putting three wafers in one rack instead of one. Six times per rack is therefore two times silicon and three times integration, which is a useful way to read the number.
How does the CS-4 connect to an existing network?
Through RoCE v2, which is RDMA over Converged Ethernet version 2, so the system attaches to standard routable Ethernet rather than a proprietary fabric or InfiniBand. That is the single most practical detail in the announcement for a network team, because it means the ingress and egress path is the same lossless Ethernet design you would build for any RDMA workload, with priority flow control and explicit congestion notification to configure. Inside the rack, Cerebras uses its own Direct Wafer Links between the three wafers, which is where the 2 microsecond figure applies. The two are separate problems. Direct Wafer Links are Cerebras business. The RoCE v2 side is yours.
What does 4,400 tokens per second per user actually measure?
It is a single user decode rate on GPT-OSS-120B, meaning the speed at which one request generates output tokens once the prompt has been processed. It is not aggregate throughput across a fleet, and the two numbers behave very differently. Tokens per second per user is what makes an interactive session or an agent loop feel fast, because an agent that plans, calls a tool and rechecks its work spends that time serially. Aggregate tokens per second across many concurrent users is what determines cost per million tokens. A system can lead on one and trail on the other, so check which figure a vendor is quoting before comparing.
Should this change how I plan inference capacity?
Not this quarter, but it is worth tracking one metric it puts pressure on, which is tokens per second per user rather than tokens per second per rack. Most serving stacks are tuned for aggregate throughput because that is what the invoice reflects. Agentic workloads invert that, since a chain of reasoning steps and tool calls runs in sequence and every step waits on decode. If your roadmap involves agents rather than chat, measure single stream decode latency on your current stack now, so you have a baseline before you evaluate anything exotic. Also note that first shipments are only expected this quarter, so there is no independent third party benchmark yet.