Kioxia and Sandisk unveiled a ninth generation 2Tb QLC 3D flash memory device on August 12, 2026, aimed squarely at AI infrastructure. The specifications that matter are a six plane architecture, four bits per cell, and a NAND interface running at 4.8 Gb/s, which the companies describe as 33 percent faster than their eighth generation part. Both bandwidth and power efficiency improve on reads and writes. The interesting engineering is the CBA architecture, where the CMOS wafer and the memory array wafer are built separately under their own optimal conditions and then bonded, which is what lets the logic get faster without disturbing the cells.
The short answer
Kioxia and Sandisk unveiled a ninth generation 2Tb QLC 3D flash memory technology on August 12, 2026, aimed at AI and data intensive infrastructure. It uses a six plane architecture and reaches a 4.8 Gb/s NAND interface speed, described as 33 percent faster than the eighth generation 2Tb QLC device, with higher read and write bandwidth and better power efficiency. Construction uses CMOS directly Bonded to Array, where logic and cell wafers are made separately and then bonded. No sampling or production date was published.
Every storage generation gets announced with a bandwidth number, and every storage generation the bandwidth number is the part least likely to describe what you will feel.
The specifications
Kioxia and Sandisk announced a ninth generation 2Tb QLC 3D flash memory technology on August 12, 2026, positioned for AI and data intensive applications. Four bits per cell, a six plane architecture, and a NAND interface speed of 4.8 Gb/s that the companies present as 33 percent above their eighth generation 2Tb QLC part. Read and write bandwidth both improve, as does read and write power efficiency.
Kioxia's CTO Hideshi Miyajima frames it as combining proven memory cell technology with the latest CMOS technology, which is a fair description of the actual engineering rather than marketing garnish. No sampling schedule, production date or pricing came with the announcement, so this is a technology unveiling and not a product you can order.
Why the two wafer trick matters
The construction method here is CMOS directly Bonded to Array, and it is the reason the interface number moved.
A NAND device is two very different machines sharing a package. There is the cell array, governed by the physics of storing charge and by a process tuned for density and retention. And there is the peripheral CMOS logic that drives it, which behaves like any other digital circuit and gets faster on a more advanced process. Building both on one wafer means every choice is a compromise between them, and historically the logic paid for it.
CBA manufactures each wafer separately, under conditions optimised for its own job, then bonds them together. That is what lets the control logic move to a faster process and push the interface to 4.8 Gb/s while the array stays on a process suited to cells. The six plane architecture is the complementary half of the same idea: planes are the unit of internal parallelism, and adding them raises the number of operations a die can have in flight, which is the practical way to raise QLC throughput given that individual QLC program operations are slow and multi pass by nature.
Reading a NAND announcement without being misled
An interface speed is a ceiling, not a delivered throughput.
The 4.8 Gb/s figure describes the link between the die and the controller. What you actually observe on a drive is set by how quickly cells program and read, how many planes are working at once, the controller and its firmware, the size and behaviour of the SLC cache, and how much garbage collection is competing with your traffic. A faster link removes one possible constraint, and it earns its keep most clearly when many dies share a channel and the channel was the limit. It does not make QLC cells program faster.
Which leads to the part that matters if you buy storage for a rack. QLC's four bits per cell is exactly what makes capacity per dollar attractive and exactly what makes endurance and sustained write performance weaker than TLC. The workloads it suits are the write once, read many kind: model weights, training datasets, media libraries, warm archival tiers. The ones it does not suit are sustained random writes, write amplifying databases, and anything with heavy metadata churn. The honest test is arithmetic, not intuition. Measure your actual daily write volume, compare it against the drive writes per day the specific drive is rated for, and note that a benchmark run against an empty SLC cache tells you nothing about hour six.
What it signals
This announcement is aimed at the same demand that is pulling half a trillion dollars of financing into AI infrastructure, and storage is the quieter half of that build out. Training and inference clusters read enormous datasets repeatedly and write comparatively little, which is the precise shape QLC handles well, so denser and more parallel QLC parts land on a real requirement rather than a manufactured one.
For everyone else, the useful reading is about the next buying cycle rather than this one. Ninth generation 2Tb dies with a faster interface point at higher capacity drives at better cost per bit arriving over the coming quarters. Without a sampling date, that is as specific as anyone can honestly be, and it is still enough to inform whether you buy your next capacity tier now or wait a cycle.
Sources and further reading
- Kioxia and Sandisk Unveil New High Performance QLC 3D Flash Memory Technology, Kioxia, August 12, 2026
- Kioxia and Sandisk Unveil 9th Gen QLC Flash for AI Infrastructure, HPCwire, August 12, 2026
- Kioxia and Sandisk Develop 2Tb Ninth Generation QLC NAND, Guru3D, August 2026
- Kioxia and Sandisk Unveil New High Performance QLC 3D Flash Memory, TechPowerUp, August 2026
- New 3D Flash Memory Technology from Kioxia and Sandisk Achieves Industry's Highest Bit Density for QLC NAND, Business Wire, August 4, 2026
Frequently asked questions
What was actually announced?
On August 12, 2026, Kioxia and Sandisk unveiled a ninth generation 2Tb QLC 3D flash memory technology, positioned for AI and data intensive workloads. The device stores four bits per cell and uses a six plane architecture. Its NAND interface runs at 4.8 Gb/s, which the companies state is a 33 percent improvement over their eighth generation 2Tb QLC part, and they claim higher read and write bandwidth plus better read and write power efficiency. The announcement is a technology unveiling: no sampling schedule, mass production date or pricing was published with it.
What does the six plane architecture change?
Planes are the unit of internal parallelism in a NAND die. Each plane can be working on its own operation, so going from fewer planes to six raises the number of reads and program operations the die can have in flight at once. That matters more for QLC than for other cell types, because QLC programming is slow and multi pass by nature, so the practical way to raise device level throughput is to overlap more operations rather than to make any single one quicker. It is a parallelism improvement, and it shows up on mixed and concurrent workloads rather than on a single threaded transfer.
What is CBA and why does it help?
CBA stands for CMOS directly Bonded to Array. Instead of building the control logic and the memory array on the same wafer in a single process, each wafer is manufactured separately under conditions optimised for what it does, and the two are then bonded together. The reason this is useful is that the two halves want incompatible things: peripheral logic benefits from an advanced fast CMOS process, while the cell array is governed by a different set of physics and process constraints. Separating them lets the interface get faster, which is where the 4.8 Gb/s figure comes from, without compromising the cells.
Should I care about QLC in a server context?
It depends entirely on your write pattern. QLC packs four bits into a cell, which is what makes the capacity per dollar attractive, and the same density is why endurance and sustained write performance are weaker than TLC. It fits read heavy workloads where data is written once and read many times, which describes model weights, training datasets, media libraries and warm archival tiers rather well. It fits poorly under sustained random writes, write amplifying databases and anything with a heavy metadata churn. Read the drive's endurance rating in drive writes per day against your measured write volume, not against your intuition.
Does a faster interface mean faster storage?
No, and this is the most common misreading of a NAND announcement. The 4.8 Gb/s figure describes the link between the NAND die and the controller, which is a ceiling rather than a delivered speed. Actual performance is set by how fast the cells program and read, how many planes are working in parallel, the controller, its SLC cache behaviour and the pressure of garbage collection. A faster interface removes one possible constraint, and it matters most when many dies share a channel, but a QLC drive with a fast interface still writes like QLC once the cache is full.
When can we buy it?
Unknown from this announcement, and that is worth stating plainly. Kioxia and Sandisk described the technology and its specifications without publishing a sampling schedule or a mass production date, and neither pricing nor specific drive products were attached to it. The industry pattern is that a device technology unveiling precedes sample shipments by some months and shipping consumer or enterprise drives by longer, so treat this as a signal about where capacity and cost per bit are heading in the next buying cycle rather than as a product you can plan a refresh around.